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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 general description the MAX17035/max17435/max17535 integrated multi- chemistry battery chargers ic simplify construction of accurate and efficient chargers. the MAX17035/ max17435/max17535 provide smbus k -programmable charge current, charge voltage, input current limit, relearn voltage, and digital readback of the iinp voltage. the MAX17035/ max17435/max17535 utilize a charge pump to control the adapter selection n-channel mosfets when the adapter is present. when the adapter is absent, the charge pump is shut down and a p-channel mosfet selects the battery. the MAX17035/max17435/max17535 provide up to 7a of charge current to 2, 3, or 4 lithium-ion (li+) cells in series. the charge current, and input current-limit sense amplifiers have low offset errors and can use 10m i sense resistors. the MAX17035/max17435/max17535 fixed-inductor ripple architecture significantly reduces component size and circuit cost. the MAX17035/max17435/max17535 provide a digital output that indicates the presence of the adapter, an analog output that indicates the adapter or battery current, depending upon the presence or absence of the adapter, and a digital output that indicates when the adapter current exceeds a user-defined threshold. the MAX17035 operates with a switching frequency of 1.2mhz. the max17435 switches at 850khz, and the max17535 switches at 500khz. the MAX17035/max17435/max17535 are available in a small, 4mm x 4mm x 0.75mm 24-pin, lead-free qfn package. an evaluation kit is available. applications notebook computers pdas and mobile communicators 2- to-4 li+ cell battery-powered devices features s low-cost smbus charger s high switching frequency (1.2mhz, 0.85mhz, 0.5mhz) s internal boost switches s smbus-programmable charge voltage, input current limit, charge current, relearn voltage, and digital iinp readback s single-point compensation s automatic selection of system power source adapter n-channel mosfets driven by an internal dedicated charge pump adapter soft-start s 0.4% accurate charge voltage s 2.5% accurate input current limiting s 3% accurate charge current s monitor outputs for ac adapter current (2% accuracy) battery discharge current (2% accuracy) ac adapter presence s ac adapter overvoltage protection s 11-bit battery voltage setting s 6-bit, charge-current setting/input current setting s improved iinp accuracy at low input current ordering information pin configuration 19-4817; rev 0; 7/09 + denotes a lead(pb)-free/rohs-compliant package. * future productcontact factory for availability. ** ep = exposed pad. smbus is a trademark of intel corp. evaluation kit available part temp range pin-package MAX17035 etg+* -40 n c to +85 n c 24 tqfn-ep** max17435 etg+ -40 n c to +85 n c 24 tqfn-ep** max17535 etg+* -40 n c to +85 n c 24 tqfn-ep** MAX17035 max17435 max17535 19 20 21 22 1 2 3 4 5 6 18 17 16 15 14 13 23 24 12 11 10 9 8 7 acin v aa ithr v cc en scl sda dcin ldo dlo adaptlim iinp cc cssn pdsl batt gnd csip acok csin dh bst lx cssp top view
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dcin, cssp, batt, csip to gnd ......................... -0.3v to +28v csip to csin, cssp to cssn .............................. -0.3v to +0.3v v cc , scl, sda, v aa , en, acin, ithr, adaptlim, acok to gnd .................................. -0.3v to +6v pdsl to gnd ......................................................... -0.3v to +37v gnd to pgnd ..................................................... -0.3v to +0.3v dhi to lx. ................................................. -0.3v to (v bst + 0.3v) bst to lx ................................................................. -0.3v to +6v bst to gnd ........................................................... -0.3v to +34v dlo to pgnd .......................................... -0.3v to (v ldo + 0.3v) lx to gnd ............................................................... -6v to +28v cc, iinp to gnd ...................................... -0.3v to (v ldo + 0.3v) ldo short circuit to gnd ......................................... momentary continuous power dissipation (t a = +70 n c) 24-pin, 4mm x 4mm thin qfn (derate 20.8mw/ n c above +70 n c) ............................ 1666mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................. +300 n c absolute maximum ratings electrical characteristics (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units input supplies adapter present quiescent current (note 1) i dcin + i cssp + i cssn + i vcc charging enabled, v adapter = 19v, v battery = 16.8v 3 6 ma charging disabled 1.5 2.2 ma batt + csip + csin + lx input current v batt = 16.8v adapter absent or charger shut down (note 1) 1.5 f a v batt = 2v to 19v, adapter present (note 1) 200 650 dcin input current i dcin charger disabled 0.7 1.0 ma v cc supply current i cc charger added 1.5 2.5 ma dcin input-voltage range for charger 8 26 v dcin undervoltage-lockout trip point for charger v dcin falling 7 7.2 v v dcin rising 7.7 7.9 dcin input-voltage range 8 24 v charge-voltage regulation battery full-charge voltage and accuracy chargingvoltage() = 0x41a0 16.733 16.8 16.867 v -0.4 +0.4 % chargingvoltage() = 0x3130 12.516 12.592 12.668 v -0.6 +0.6 % chargingvoltage() = 0x20d0 8.333 8.4 8.467 v -0.8 +0.8 % chargingvoltage() = 0x1060 4.15 4.192 4.234 v -1.0 +1.0 % battery undervoltage-lockout trip point for trickle charge 3 3.5 4 v
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units charge-current regulation csip-to-csin full-scale current-sense voltage 78.22 80.64 83.06 mv charge current and accuracy rs2 = 10m i , figure 1; chargingcurrent()= 0x1f80 7.822 8.064 8.306 a -3 +3 % rs2 = 10m i , figure 1; chargingcurrent()= 0x0f80 3.829 3.968 4.107 a -3.5 +3.5 % rs2 = 10m i , figure 1; chargingcurrent()= 0x0080 64 128 192 ma -50 +50 % charge-current gain error based on chargecurrent() = 128ma and 8.064a -2 +2 % input current regulation input current-limit threshold rs1 = 10m w , figure 1, inputcurrent() = full scale 106.7 110 113.3 mv -2.5 +2.5 % rs1 = 10m w , figure 1, inputcurrent() = 0c80 62.08 64 65.92 mv -3 +3 % rs1 = 10m w , figure 1, inputcurrent() = 0780 36.86 38.4 39.94 mv -4 +4 % cssp/cssn input-voltage range 8 26 v iinp voltage gain 19.7 19.85 20.3 v/v iinp output-voltage range 0 4.2 v iinp accuracy v cssp - v cssn = 110mv -5 +5 % v cssp - v cssn = 55mv -4 +4 v cssp - v cssn = 5mv -10 +10 iinp gain error based on v cssp - v cssn = 110mv and v cssp - v cssn = 55mv -1.5 +1.5 % iinp offset error based on v cssp - v cssn = 110mv and v cssp - v cssn = 55mv -350 +350 f v reference ref output voltage ref i ref = 50 f a 4.082 4.096 4.115 v ref undervoltage-lockout threshold ref falling 3.1 3.9 v linear regulator ldo output voltage ldo i ref = 50 f a 5.25 5.4 5.6 v ldo load regulation 0 < i ldo < 40ma 127 250 mv ldo undervoltage-lockout threshold ldo falling 3.2 4.1 5.0 v
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 4 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units acok acok sink current v acok = 0.4v, acin = 2.5v 1 ma acok leakage current v acok = 5.5v, acin = 0.5v, t a = +25 n c 1 f a acin acin threshold 1.465 1.485 1.53 v acin threshold hysteresis 20 mv acin falling delay 10 f s acin input-bias current t a = +25 n c -1 +1 f a ithr/adaptlim ithr leakage current v ithr = 0v to ldo, t a = +25 n c -1 +1 f a adaptlim sink current v ithr > v iinp 1 ma adaptlim leakage current v ithr < v iinp, t a = +25 n c 1 f a ithr threshold calculated = v ithr - v iinp -12 +12 mv logic levels sda/scl input low voltage 0.8 v sda/scl input high voltage 2.1 v sda/scl input-bias current t a = +25 n c -1 +1 f a switching regulator dhi off-time k factor v dcin = 19v, v batt = 10v, MAX17035 29 35 41 ns/v v dcin = 19v, v batt = 10v, max17435 47 52 57 v dcin = 19v, v batt = 10v, max17535 80 87 94 sense voltage for minimum discontinuous mode ripple current v csip - v csin 5 mv zero-crossing comparator threshold v csip - v csin 5 mv cycle-by-cycle current-limit sense voltage v csip - v csin 120 125 130 mv dhi resistance high i dhi = 10ma 1.5 3 i dhi resistance low i dhi = -10ma 0.8 1.6 i dlo resistance high i dlo = 10ma 3 6 i dlo resistance low i dlo = -10ma 3 6 i adapter detection adapter absence detect threshold v dcin - v batt , v dcin falling 50 120 200 mv adapter detect threshold v dcin - v batt , v dcin rising 340 430 600 mv charge-pump mosfet driver pdsl gate-driver source current v pdsl - v dcin = 3v, v dcin = 19v 40 64 f a pdsl gate-driver output voltage high v dcin = 19v, open load v dcin + 5.3 v dcin + 8 v
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) electrical characteristics (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min typ max units adapter overvoltage protection acovp threshold rising 2.04 2 2.1 v acovp threshold hysteresis 30 mv adapter overcurrent protection acocp threshold with respect to v cssp - v cssn 144 mv acocp blanking time 16 ms acocp waiting time when acocp comparator is high and at the time the blanking time expires 0.6 s pdsl switch control pdsl turn-off resistance 2.5 4 k i smbus timing specifications smbus frequency f smb 10 100 khz bus free time t buf 4.7 f s start condition hold time from scl t hd:sta 4 f s start condition setup time from scl t su:sta 4.7 f s stop condition setup time from scl t su:sto 4 f s holdup time from scl t hd:dat 300 ns setup time from scl t su:dat 250 ns scl low period t low 4.7 f s scl high period t high 4 f s maximum charging period without a charge_voltage() or chargecurrent() command 140 175 210 s parameter symbol conditions min max units input supplies adapter present quiescent current i dcin + i cssp + i cssn (note 1) charging enabled, v adapter = 19v, v battery = 16.8v 6 ma charging disabled 2.2 ma
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 6 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min max units batt + csip + csin + lx input current v batt = 16.8v adapter absent or charger shut down (note 1) 1.5 f a v batt = 2v to 19v, adapter present (note 1) 650 dcin input current i dcin charger disabled 1 ma dcin standby supply current dcin = 5v to 26v 300 f a vcc supply current i cc charger enabled 2.5 ma dcin input-voltage range for charger 8 26 v dcin undervoltage-lockout trip point for charger v dcin falling 7 v v dcin rising 7.9 dcin input-voltage range 8 24 v charge-voltage regulation battery full-charge voltage and accuracy chargingvoltage() = 0x41a0 16.73 16.87 v -0.416 +0.416 % chargingvoltage() = 0x3130 12.516 12.668 v -0.6 +0.6 % chargingvoltage() = 0x20d0 8.333 8.467 v -0.8 +0.8 % chargingvoltage() = 0x1060 4.15 4.234 v -1.0 +1.0 % battery undervoltage-lockout trip point for trickle charge 3 4 v charge-current regulation csip-to-csin full-scale current-sense voltage 78.22 83.06 mv charge current and accuracy rs2 = 10m i , figure 1; chargingcurrent() = 0x1f80 7.822 8.306 a -3 +3 % rs2 = 10m i , figure 1; chargingcurrent()= 0x0f80 3.829 4.107 a -3.5 +3.5 % rs2 = 10m i , figure 1; chargingcurrent() = 0x0080 64 192 ma -50 +50 % charge-current gain error based on chargecurrent() = 128ma and 8.064a -2 +2 %
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min max units input current regulation input current-limit threshold rs1 = 10m i , figure 1; inputcurrent() = full scale 106.7 113.3 mv -2.5 +2.5 % rs1 = 10m i , figure 1; inputcurrent()= 0c80 62.08 65.92 mv -3 +3 % rs1 = 10m i , figure 1; inputcurrent()= 0780 36.86 39.94 mv -4 +4 % cssp/cssn input voltage range 8 26 v iinp voltage gain 19.7 20.3 % iinp output-voltage range 0 4 v iinp accuracy v cssp - v cssn = 110mv -5 +5 % v cssp - v cssn = 55mv -4 +4 v cssp - v cssn = 5mv -10 +10 iinp gain error based on v cssp - v cssn = 100mv and v cssp - v cssn = 20mv -1 +1 % iinp offset error based on v cssp - v cssn = 100mv and v cssp - v cssn = 5mv -500 +500 f v reference ref output voltage ref i ref = 50 f a 4.075 4.115 v ref undervoltage- lockout threshold ref falling 3.9 v linear regulator ldo output voltage ldo i ref = 50 f a 5.25 5.6 v ldo load regulation 0 < i ldo < 40ma 250 mv ldo undervoltage-lockout threshold ldo falling 3.2 5.0 v acok acok sink current v acok = 0.4v, acin = 2.5v 1 ma acin acin threshold 1.465 1.53 v acin threshold hysteresis 30 50 mv acin input-bias current -1 +1 f a ithr/adaptlim ithr leakage current v ithr = 0 to 5.4v 1 f a adaptlim sink current v ithr > v iinp 1 ma adaptlim leakage current v ithr < v iinp 1 f a ithr threshold calculated = v ithr - v iinp -12 +12 mv
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 8 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = -40 c to +85 c , unless otherwise noted.) (note 2) parameter symbol conditions min max units logic levels sda/scl input low voltage 0.8 v sda/scl input high voltage 2.1 v sda/scl input-bias current -1 f a switching regulator dhi off-time k factor v dcin = 19v, v batt = 10v, MAX17035 29 41 ns/v v dcin = 19v, v batt = 10v, max17435 47 57 v dcin = 19v, v batt = 10v, max 17535 80 94 cycle-by-cycle current-limit sense voltage v csip - v csin 120 130 mv dhi resistance high i dhi = 10ma 3 i dhi resistance low i dhi = -10ma 1.6 i dlo resistance high i dlo = 10ma 6 i dlo resistance low i dlo = -10ma 6 i adapter detection adapter absence detect threshold v dcin - v batt , v dcin falling 50 200 mv adapter detect threshold v dcin - v batt , v dcin rising 340 570 mv charge-pump mosfet driver pdsl gate-driver output-voltage high v dcin = 19v v dcin + 5.3 v adapter overvoltage protection acovp threshold rising 2.04 2.1 v pdsl switch control pdsl turn-off resistance 4 k i smbus timing specifications smbus frequency f smb 10 100 khz bus free time t buf 4.7 f s start condition hold time from scl t hd:sta 4 f s start condition setup time from scl t su:sta 4.7 f s stop condition setup time from scl t su:sto 4 f s
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 _______________________________________________________________________________________ 9 electrical characteristics (continued) (circuit of figure 1, no load on ldo, v dcin = v cssp = v cssn = 19v, v lx = 0v, v bst - v lx = 5v, v batt = v csip = v csin = 16.8v, t a = -40 c to +85 c , unless otherwise noted.) (note 2) note 1: adapter present conditions are tested at v dcin = 19v and v batt = 16.8v. adapter absent conditions are tested at v dcin = 16v, v batt = 16.8v. note 2: specifications to -40c are guaranteed by design and not production tested. typical operating characteristics (circuit of figure 1, v in = 19v, v cc = v dd = 5v, en = v cc , t a = +25 n c, unless otherwise specified.) input current-limit error vs. input current-limit setting MAX17035 toc01 input current-limit setting (a) input current-limit error (%) 6 4 2 -2 0 2 4 6 8 10 12 14 16 -4 0 8 input current-limit error vs. system current MAX17035 toc02 system current (a) input current-limit error (%) 3 2 1 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -4.0 0 4 v batt = 16.8v input current limit = 3.584a v batt = 12.6v v batt = 8.4v iinp error vs. system current (dc sweep) MAX17035 toc03 v cssp - v cssn (mv) iinp error (%) 40 20 0 5 10 15 20 25 30 -5 0 60 v adapter = 0v, v batt = 15v v adapter = 20v parameter symbol conditions min max units hold time from scl t hd:dat 300 ns setup time from scl t su:dat 250 ns scl low period t low 4.7 f s scl high period t high 4 f s maximum charging period without a charge_voltage() or chargecurrent() command 140 210 s
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 10 _____________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 19v, v cc = v dd = 5v, en = v cc , t a = +25 n c, unless otherwise specified.) iinp error vs. system current MAX17035 toc04 system current (a) iinp error (%) 3 2 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -5.0 0 4 input current limit = 3.584a v batt = 16.8v v batt = 12.6v v batt = 8.4v charger-current error vs. battery voltage MAX17035 toc05 battery voltage (v) charger-current error (%) 13 8 0 0.5 1.0 1.5 2.0 2.5 3.0 -0.5 3 18 i charger = 5a i charger = 4a i charger = 3a charger-current error vs. smbs setting MAX17035 toc06 input current-limit setting (a) charger-current error (%) 4 2 1 2 3 4 5 6 7 8 9 0 6 charge voltage accuracy at 3.854a MAX17035 toc07 charge voltage (v) error (%) 15 10 5 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.15 0 20 charger voltage error vs. charger current MAX17035 toc08 charger current (a) charger voltage error (%) 4 2 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.7 0 6 v batt = 16.8v v batt = 8.4v v batt = 12.6v battery removal (v batt = 3v ) MAX17035 toc09 il 1a/div pdsl 5v/div v batt 5v/div dcin 5v/div 100fs/div system load transient (0a 3a 0a ) MAX17035 toc10 i sysld 1a/div il 1a/div v batt 200mv/div cc 1v/div 1ms/div charge-output short circuit MAX17035 toc11 20fs/div il 2a/div 0a v batt 5v/div efficiency vs. charge current (2, 3, and 4 cells) MAX17035 toc12 charge current (a) efficiency (%) 5 4 3 2 1 55 60 65 70 75 80 85 90 95 100 50 0 6 4 cell 3 cell 2 cell
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 11 typical operating characteristics (continued) (circuit of figure 1, v in = 19v, v cc = v dd = 5v, en = v cc , t a = +25 n c, unless otherwise specified.) ldo voltage vs. ldo current MAX17035 toc13 ldo current (ma) ldo voltage (v) 40 30 20 10 5.36 5.38 5.40 5.42 5.44 5.46 5.48 5.34 0 50 v aa deviation, switching and not switching MAX17035 toc14 dcin (v) deviation (mv) 25 20 5 10 15 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 30 not switching switching v aa vs. temperature MAX17035 toc15 temperature (nc) v aa voltage (v) 80 60 40 20 0 -20 4.085 4.090 4.095 4.100 4.105 4.110 4.080 -40 100 frequency vs. v batt at 4a i chg MAX17035 toc16 v batt (v) frequency (khz) 15 10 5 100 200 300 400 500 600 700 800 900 1000 0 0 20 power-source selector scheme with battery present (adapter removal) MAX17035 toc17 10ms/div pdsl 5v/div v adapter 5v/div v sysld 5v/div v batt 5v/div power-source selector scheme with battery present (adapter insertion) MAX17035 toc18 40ms/div pdsl 5v/div v sysld 5v/div v adapter 5v/div v batt 5v/div
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 12 _____________________________________________________________________________________ pin description pin name function 1 scl smbus clock input. connect to an external pullup resistor according to smbus specifications. 2 sda smbus data i/o. open-drain output. connect to an external pullup resistor according to smbus specifications. 3 dcin charger supply input. connect to adapter supply. for minimum input bias current connect to the center of the input/soft-start fets. bypass with a 1 f f ceramic capacitor to pgnd placed close to the pin. add a 10 w resistor to reduce input surge at adapter insertion. 4 ldo linear regulator output. this is a 30ma reference and also powers the dlo driver, the bst circuit, and the internal smbus circuitry. bypass with a 1 f f ceramic capacitor to pgnd placed close to the pin. this output is disabled when the charger is disabled. 5 dlo low-side power-mosfet driver output. connect to low-side n-channel mosfet gate. 6 adaptlim adaptive system current-limit comparator output. this open-drain output is high impedance when the voltage at the iinp pin is lower than the ithr threshold. for a typical application, use a 10k w pullup resistor to ldo (pin 4). 7 bst high-side driver supply. connect a 0.1 f f capacitor from bst to lx. 8 lx high-side driver source connection 9 dhi high-side power mosfet driver output. connect to high-side n-channel mosfet gate. 10 acok ac detect output .this open-drain output is high impedance when acin is lower than 1.5v. the acok output remains high when the MAX17035/max17435/max17535 are powered down. for a typical application, use a 10k i pullup resistor to ldo (pin 4). 11 csin output current-sense negative input. connect this pin to the negative terminal of the sense resistor. see the setting charge current section for resistor value and scaling. 12 csip output current-sense positive input. connect a current-sense resistor from csip to csin; the voltage across these two pins is interpreted by the MAX17035/max17435/max17535 as proportional to the charge current delivered to the battery with approximately 110mv full-scale voltage. see the setting charge current section for resistor value and scaling. 13 batt battery voltage feedback input. connect as close as possible to the battery terminal. 14 pdsl power-source n-channel mosfet switch driver output. when the adapter is not present or an overvoltage event detected at the input, the pdsl output is pulled to gnd with a 2.5k w (typ) resistor. otherwise, it is typically 8v above the adapter voltage when the part is not using the battery. this is powered by an internal charge pump. 15 cssn input current-sense negative input. see the description of the cssp pin for resistor value and scaling. 16 cssp current sense for positive input. connect a current-sense resistor from cssp to cssn. the voltage across cssp to cssn determines the current at which the charger reduces charging current to keep from drawing more current from the adapter than is allowed. as the system current flowing in the resistor from cssn to cssp increases, the charger reduces charge current to keep the system current at the limit value. when the system current reaches approximately 130% of the max programmed value, the pdsl pin changes state and turns off the input fet to prevent excess current from the adapter. when the adapter overcurrent condition occurs, give a 16ms blanking time, and then turn off the adapter switch. the adapter switch is turned on again after 0.6s. try the same thing one more time. after the third blanking time (16ms), the adapter mosfets are latched in the off state. to release the adapter switchs off state, adapter removal and reinsertion is needed.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 13 pin description (continued) pin name function 17 cc voltage regulation loop-compensation point. connect a 10nf capacitor from cc to gnd. 18 iinp input current-monitor output. the voltage at the iinp pin is 20 times the voltage from cssp to cssn. this voltage is present when charging is enabled to monitor the system current, and when the battery is discharging to monitor the battery discharge current. 19 acin ac adapter-detect input. acin is the input to a comparator with a comparison voltage of about 1.5v. the output of the comparator is acok . acok goes low when the threshold voltage is exceeded to indicate that the ac adapter is present, and it enables the charger. when the acin input is above 2.1v, the MAX17035/max17435/max17535 interpret that as an adapter overvoltage event. the charger is then disabled and the adapter mosfets are turned off. if the part is charging and the acin voltage drops below the programmed threshold, the charger is disabled and a chargecurrent() and chargevoltage() command have to be written over the smbus to reenable the charger. 20 ithr adaptive system current-limit comparator threshold. this pin connects to the inverting input of a comparator. the noninverting input of the comparator is the iinp input, while the output is driving the adaptlim open drain. when the input to ithr is greater than iinp, the adaptlim output is high. 21 v aa 4.096v internal reference voltage; no external load allowed. bypass to analog ground using a 1 f f or greater ceramic capacitor. 22 v cc circuitry supply-voltage input. connect to ldo through 10 i and bypass with a 0.1 f f capacitor to gnd as close as possible to the package pin. 23 gnd analog ground 24 en enable/disable charger operation. this disables the charger and associated circuitry when en goes low and is in addition to the acok charger enable. if the adapter is absent and en is pulled up to a voltage higher than 2.4v, the battery-discharge current monitor on iinp is enabled. ep exposed pad. connect backside exposed pad to power ground.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 14 _____________________________________________________________________________________ figure 1. standard application circuit detailed description the MAX17035/max17435/max17535 charger includes all the functions necessary to charge li+, nimh, and nicd smart batteries. a high-efficiency synchronous rectified step-down dc-dc converter is used to implement a constant-current constant-voltage charger. the dc-dc converter drives a high-side n-channel mosfet and provides synchronous rectification with a low-side n-channel mosfet. the charge current and input current-sense amplifiers have low-input offset errors (200 f v typ), allowing the use of small-valued sense resistors. the MAX17035/max17435/max17535 use an smbus interface similar to the max8731a to set charge current, charge voltage, and input current limit. in addition, the MAX17035/max17435/max17535 smbus interface supports relearn(), and iinpvoltage() readback. b attery a dapter b s t c s s p c s s n d h i l x d l o p g n d p a d c s i n c s i p b a t t c c s c l l d o g n d i i n p v aa v cc c in n1 n2 n3 n4 l1 s ystem load c in = 2 x 4.7ff c out = 4.7ff l1 = 2fh r9 2mi r4 150ki c6 10nf rs1 10mi c10 1ff c4 0.1ff c5 0.01ff rs2 10mi r7 10ki r8 49.9ki r6 7.06ki r9 103ki r10 10ki r5 10ki r16 10i q1a q1b a c i n a c o k s d a en d c i n p d s l g n d i t h r a d a p t l i m l d o l d o l d o r12 10ki i i n p v oltage a dapter current limit flag s m b u s control a c o k l d o MAX17035 r17 10i r18 1ki r14 10ki r13 10ki c out c1 1ff c3 1ff c11 1ff c2 0.1ff
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 15 figure 2. block diagram the MAX17035/max17435/max17535 control input current (ccs control loop), charge current (cci control loop), or charge voltage (ccv control loop), depending on the operating condition. the three control loops, ccv, cci, and ccs, are brought together internally at the lowest voltage clamp (lvc) amplifier. the output of the lvc amplifier is the feedback control signal for the dc-dc controller. the minimum voltage at the ccv, cci, or ccs appears at the output of the lvc amplifier and clamps the other control loops to within 0.3v above the control point. clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the compensation section). the cci loop is internally compensated and the ccv and ccs loops share a common compensation network at cc. the dominant control loop (ccv, ccs) drives the compensation network. c s s n c s s p iinp pgnd ldo ldo dlo pgnd bst dhi lx c urrent- sense amplifier c urrent- sense amplifier c s i n c s i p c si b a t t c harge voltage() +200mv 5.4v regulator gm v s c l 11-b it d a c v c t l 6-b it iset 7-b it in_set 6-bit readback smbu s l ogic ac ovp imax 12a ccmp imin zcmp 128ma d c-dc converter battery c c lvc and cap switch logic c h a r g e v o l t a g e() relearn() charge current() input current() s d a in_s e t a dapter present high-side driver d c i n c s i n b d i v d c i n 1.5v acin acok ithr pdsl 4.096v r eference v a a p d s l l ogic a c_en a c_en a = 20v/v e n a d a p t l i m g m i g m s c h g_en MAX17035 low-side driver iinp
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 16 _____________________________________________________________________________________ table 1. en pin function en pin the en pin is a logic input. the state of the en pin and the presence or absence of the adapter determines the state of pdsl, the iinp path, and the charger function as shown in table 1. 30ma ldo the 5.4v ldo is powered from dcin and is compensated for loads from 0 to 30ma with a single 1 f f ceramic capacitor. the load regulation over the 30ma load is 34mv (typ), 100mv max. the ldo supplies the drive for the dlo driver and also the bst circuitry. it is shut down when the adapter is absent. analog input current monitor output iinp monitors the system-input current sensed across the sense resistor (rs1) that connects between cssp and cssn. the voltage at iinp is proportional to the input current according to the following equation: iinp input v i rs1 a = where i input is the dc current supplied by the ac adapter and a is the gain (20v/v typ). iinp has a 0v to 2.2v output-voltage range. table 1 shows the charge and iinp status when the adapter is present or absent and as a function of the en pin. when connected as shown in the standard application circuit, iinp monitors the input system current when the adapter is present or the battery discharge current when the adapter is absent. leave iinp unconnected if not used. table 2 is the fault-protection and shutdown operation table. smbus implementation the MAX17035/max17435/max17535 receive control inputs from the smbus interface. the MAX17035/max17435/ max17535 use a subset of the commands documented in the system management bus specifications v2.0, which can be downloaded from www.smbus.org . the MAX17035/max17435/max17535 use the smbus read- word and write-word protocols to communicate with the system controller. the MAX17035/max17435/max17535 operate only as slave devices with address 0b0001001_ (0x12) and do not initiate communication on the bus. in addition, the MAX17035/max17435/max17535 have two identification registers: (0xfe), a 16-bit device id register and a 16-bit manufacturer id register (0xff). the smbus implementation is similar to the max8731a with the addition of the relearn() and iinpvoltage() commands. the smbus is not powered from an external supply, so during states that disable the charger, the smbus register data is lost, so the register data must be rewritten when reenabled. see figure 3. the data (sda) and clock (scl) pins have schmitt- trigger inputs that can accommodate slow edges. choose pullup resistors for sda and scl to achieve rise times according to the smbus specifications. communication starts when the master signals a start condition, which is a high-to-low transition on sda, while scl is high. when the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on sda, while scl is high. the bus is then free for another transmission. table 2. fault protection and shutdown operation table adapter present en pdsl status charger status system current monitor status (iinp path) yes high pdsl is pumped 8v above the dcin voltage (charge pump on). enabled enabled yes low pdsl is pumped 8v above the dcin voltage (charge pump on). disabled enabled no high charge pump is off and pdsl is forced to 0v (typ, 27c). disabled enabled no low charge pump is off and pdsl is forced to 0v (typ, 27c). disabled disabled mode controller state driver state thermal fault (latched, reset with adapter insertion) charger disabled dhi and dlo low
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 17 figure 3. smbus write-word and read-word protocols figure 4. smbus write timing figures 4 and 5 show the timing diagrams for signals on the smbus interface. the address byte, command byte, and data bytes are transmitted between the start and stop conditions. the sda state is allowed to change only while scl is low, except for the start and stop conditions. data is transmitted in 8-bit bytes and is sampled on the rising edge of scl. nine clock cycles are required to transfer each byte in or out of the MAX17035/ max17435/max17535 because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. the MAX17035/max17435/max17535 support the charger commands as described in table 4. s a) write-word format w ack ack ack p command byte low data byte high data byte slave address ack 7 bits 8 bits 1b msb lsb msb lsb 8 bits msb lsb 8 bits msb lsb 0 1b 0 1b 0 1b 0 1b 0 preset to 0b0001001 relearn () = 0x3d chargingcurrent() = 0x14 chargervoltage() = 0x15 inp_voltage () = 0x3e d7 d0 d15 d8 s b) read-word format w ack ack nack p command byte low data byte high data byte slave address s ack 7 bits 8 bits 1b msb lsb slave address 7 bits msb lsb msb lsb 8 bits msb lsb 8 bits msb lsb 0 1b 0 r ack 1b 1 1b 0 1b 0 1b 0 1b 1 preset to 0b0001001 preset to 0b0001001 d7 d0 d15 d8 legend: s = start condition or repeated start condition ack = acknowledge (logic-low) w = write bit (logic-low) p = stop condition nack = not acknowledge (logic-high) r = read bit (logic-high) master to slave slave to master smbclk a b c d e f g h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low l m f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = slave pulls smbdata line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 18 _____________________________________________________________________________________ battery charger commands the MAX17035/max17435/max17535 support four battery-charger commands that use either write-word or read-word protocols as summarized in table 3. manufacturerid() and deviceid() can be used to identify the MAX17035/max17435/max17535. on the MAX17035/ max17435/max17535 manufacturerid() always returns 0x004d and deviceid() always returns 0x0008. setting charge voltage to set the output voltage, use the smbus to write a 16-bit chargevoltage() command using the data format listed in table 4. the chargevoltage() command uses the write-word protocol (see figure 3). the command code for chargevoltage() is 0x15 (0b00010101). the MAX17035/max17435/max17535 provide a charge- voltage range of 4.095v to 19.200v, with 16mv resolution. set chargevoltage() below 4.095v to terminate charging. upon reset, the chargevoltage() and chargecurrent() values are cleared and the charger remains off until both the chargevoltage() and the chargecurrent() command are sent. both dhi and dlo remain low until the charger is restarted. setting charge current to set the charge current, use the smbus to write a 16-bit chargecurrent() command using the data format listed in table 5. the chargecurrent() command uses the write-word protocol (see figure 3). the command code for chargecurrent() is 0x14 (0b00010100). when rs2 = 10m i , the MAX17035/max17435/max17535 provide a charge- current range of 128ma to 11.004a, with 128ma resolution. if a sense resistor other than 10m i is used, the current limit must be scaled by rs/10m i , where rs is the sense resistor value used on the circuit. set chargecurrent() to 0 to terminate charging. upon reset, the chargevoltage() and chargecurrent() values are cleared and the charger remains off until both the chargevoltage() and the chargecurrent() command are sent. both dhi and dlo remain low until the charger is restarted. the MAX17035/max17435/max17535 include a fault limiter for low-battery conditions. if the battery voltage is less than 3v, the charge current is temporarily set to 128ma. the chargecurrent() register is preserved and becomes active again when the battery voltage is higher than 3v. this function effectively provides a foldback current limit that protects the charger during short circuit and overload. figure 5. smbus read timing table 3. battery charger command summary smbclk a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave a b c d e f g h i j smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:dat t su:sto t buf k e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = acknowledge clock pulse j = stop condition k = new start condition command command name read/write description por state 0x14 chargecurrent() write only 6-bit charge-current setting 0x0000 0x15 chargevoltage() write only 11-bit charge-voltage setting 0x0000 0x3d relearn voltage read and write 11-bit relearn voltage set and 1 bit enable/status 0x4b00 0x3e iinpvoltage() read only digital read of iinp voltage na 0x3f inputcurrent() write only 6-bit charge-current setting 0x0080 0xfe manufacturerid() read only manufacturer id 0x004d 0xff deviceid() read only device id 0x0008
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 19 table 4. chargevoltage() (0x15) table 5. chargecurrent() (0x14) (10m i sense resistor, rs2) bit bit name description 0 not used. normally a 1mv weight. 1 not used. normally a 2mv weight. 2 not used. normally a 4mv weight. 3 not used. normally an 8mv weight. 4 charge voltage, dacv 0 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 16mv of charger voltage compliance. 5 charge voltage, dacv 1 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 32mv of charger voltage compliance. 6 charge voltage, dacv 2 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 64mv of charger voltage compliance. 7 charge voltage, dacv 3 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 128mv of charger voltage compliance. 8 charge voltage, dacv 4 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 256mv of charger voltage compliance. 9 charge voltage, dacv 5 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 512mv of charger voltage compliance. 10 charge voltage, dacv 6 0 = adds 0ma of charger voltage compliance, 4095mv min. 1 = adds 1024mv of charger voltage compliance. 11 charge voltage, dacv 7 0 = adds 0mv of charger voltage compliance, 4095mv min. 1 = adds 2048mv of charger voltage compliance. 12 charge voltage, dacv 8 0 = adds 0mv of charger voltage compliance. 1 = adds 4096mv of charger voltage compliance. 13 charge voltage, dacv 9 0 = adds 0mv of charger voltage compliance. 1 = adds 8192mv of charger voltage compliance. 14 charge voltage, dacv 10 0 = adds 0mv of charger voltage compliance. 1 = adds 16384mv of charger voltage compliance, 19200mv max. 15 not used. normally a 32768mv weight. bit bit name description 0 not used. normally a 1ma weight. 1 not used. normally a 2ma weight. 2 not used. normally a 4ma weight. 3 not used. normally an 8ma weight. 4 not used. normally a 16ma weight. 5 not used. normally a 32ma weight. 6 not used. normally a 64ma weight. 7 charge current, daci 0 0 = adds 0ma of charger current compliance. 1 = adds 128ma of charger current compliance. 8 charge current, daci 1 0 = adds 0ma of charger current compliance. 1 = adds 256ma of charger current compliance.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 20 _____________________________________________________________________________________ setting input-current limit system current normally fluctuates as portions of the system are powered up or put to sleep. by using the input- current-limit circuit, the output-current requirement of the ac wall adapter can be lowered, reducing system cost. the total input current is the sum of the system supply current, the charge current flowing into the battery, and the current required by the charger. when the input current exceeds the input current limit set with the inputcurrent() command, the MAX17035/max17435/ max17535 reduce the charge current to provide priority to system load current. as the system supply current increases, the charge current is reduced as needed to maintain the total input current at the input current limit. the MAX17035/max17435/max17535 decrease the charge current to zero, if necessary, to reduce the input current to the input current limit. thereafter, if the system current continues to increase, there is nothing the MAX17035/max17435/max17535 can do to maintain the input current at the input current limit. if the system current continues to increase the total input current can increase until the acocp threshold (which is 1.3 x maximum dac setting) is reached and the MAX17035/max17435/ max17535 drive pdsl low to remove the input voltage. the MAX17035/max17435/max17535 wait 0.6s and then try to charge again; after a 16ms blanking period if the current is again over the acocp threshold, it again opens up the input voltage. it goes through this cycle three times; after three times, the MAX17035/max17435/ max17535 wait for the adapter voltage to be removed and reinserted before it reconnects the input voltage. the total input current can be estimated as follows: input system charger charge battery in i i i [(i v ) (v )] = + + where e is the efficiency of the dc-dc converter (typically 85% to 95%). to set the input current limit, issue the smbus command inputcurrent() using the 16-bit data format listed in table 6. the inputcurrent() command uses the write- word protocol (see figure 3). the command code for inputcurrent() is 0x3f (0b00111111). when rs1 = 10m i , the MAX17035/max17435/max17535 provide an input current-limit range of 256ma to 11.004a with 256ma resolution. if a resistor rs other than 10m i is used, the input current limit is scaled by a factor of 10m i /rs1. inputcurrent() settings from 1ma to 128ma result in a current limit of 128ma. upon reset, the input current limit is 128ma. setting relearn voltage to set the relearn voltage issue, the smbus command relearnvoltage() uses the 16-bit data format listed in table 7. the relearnvoltage() command uses the write-word and read-word protocols (see figure 3). the command code for relearnvoltage() is 0x3d (0b00111101). the MAX17035/max17435/max17535 provide a charge-voltage range of 4.095v to 19.200v with 16mv resolution. when the relearn function is enabled by setting bit 0 to 1, the pdsl pin switches off the input-voltage fet and switches on the battery fet, enabling discharging of the battery. the battery voltage is monitored until the battery voltage reaches the relearn voltage and thus a known low state of charge. the pdsl state is then reset to allow charging and bit 0 is set to zero. table 5. chargecurrent() (0x14) (10m i sense resistor, rs2) (continued) bit bit name description 9 charge current, daci 2 0 = adds 0ma of charger current compliance. 1 = adds 512ma of charger current compliance. 10 charge current, daci 3 0 = adds 0ma of charger current compliance. 1 = adds 1024ma of charger current compliance. 11 charge current, daci 4 0 = adds 0ma of charger current compliance. 1 = adds 2048ma of charger current compliance. 12 charge current, daci 5 0 = adds 0ma of charger current compliance. 1 = adds 4096ma of charger current compliance, 8064ma max 13 not used. normally a 8192ma weight. 14 not used. normally a 16386ma weight. 15 not used. normally a 32772ma weight.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 21 table 6. inputcurrent() (0x3f) (10m i sense resistor, rs1) table 7. relearn() (0x3d) bit bit name description 0 not used. normally a 2ma weight. 1 not used. normally a 4ma weight. 2 not used. normally an 8ma weight. 3 not used. normally a 16ma weight. 4 not used. normally a 32ma weight. 5 not used. normally a 64ma weight. 6 not used. normally a 128ma weight. 7 input current, dacs 0 0 = adds 0ma of input current compliance. 1 = adds 256ma of input current compliance. 8 input current, dacs 1 0 = adds 0ma of input current compliance. 1 = adds 512ma of input current compliance. 9 input current, dacs 2 0 = adds 0ma of input current compliance. 1 = adds 1024ma of input current compliance. 10 input current, dacs 3 0 = adds 0ma of input current compliance. 1 = adds 2048ma of input current compliance. 11 input current, dacs 4 0 = adds 0ma of input current compliance. 1 = adds 4096ma of input current compliance. 12 input current, dacs 5 0 = adds 0ma of input current compliance. 1 = adds 8192ma of input current compliance, 11004ma max. 13 not used. normally a 16384ma weight. 14 not used. normally a 32768ma weight. 15 not used. normally a 65536ma weight. bit bit name description 0 relearn, rl 0 0 = disables the relearn function. 1 = enables the relearn function. when the relearn threshold is crossed as the battery discharges, bit 0 is reset to zero by the MAX17035/max17435/max17535. 1 not used. 2 not used. 3 not used. 4 relearn, rl 1 0 = adds 0mv of relearn threshold compliance, 1024 mv min. 1 = adds 16mv of relearn threshold compliance. 5 relearn, rl 2 0 = adds 0mv of relearn threshold compliance, 1024 mv min. 1 = adds 32mv of relearn threshold compliance. 6 relearn, rl 3 0 = adds 0mv of relearn threshold compliance, 1024 mv min. 1 = adds 64mv of relearn threshold compliance. 7 relearn, rl 4 0 = adds 0mv of relearn threshold compliance, 1024 mv min. 1 = adds 128mv of relearn threshold compliance. 8 relearn, rl 5 0 = adds 0mv of relearn threshold compliance, 1024 mv min. 1 = adds 256mv of relearn threshold compliance.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 22 _____________________________________________________________________________________ reading iinp voltage to read the digital version of the iinp voltage, issue the smbus command iinpvoltage() command using the 16 bit data format listed in table 8. the command code for iinpvoltage() is 0x3e (0b00111110). the iinpvoltage() command uses the read-word protocol (see figure 3). charger timeout the MAX17035/max17435/max17535 include a timer to terminate charging if the charger has not received a chargevoltage() or chargecurrent() command within 175s. if a timeout occurs, both chargevoltage() and chargecurrent() commands must be sent again to reenable charging. table 7. relearn() (0x3d) (continued) table 8. iinpvoltage() (0x3e) bit bit name description 9 relearn, rl 6 0 = adds 0mv of relearn threshold compliance, 1024 mv min. 1 = adds 512mv of relearn threshold compliance. 10 relearn, rl 7 0 = adds 0ma of relearn threshold compliance. 1 = adds 1024mv of relearn threshold compliance. 11 relearn, rl 8 0 = adds 0mv of relearn threshold compliance. 1 = adds 2048mv of relearn threshold compliance. 12 relearn, rl 9 0 = adds 0mv of relearn threshold compliance. 1 = adds 4096mv of relearn threshold compliance. 13 relearn, rl 10 0 = adds 0mv of relearn threshold compliance. 1 = adds 8192mv of relearn threshold compliance. 14 relearn, rl 11 0 = adds 0mv of relearn threshold compliance. 1 = adds 16384mv of relearn threshold compliance, 19200mv max. 15 not used. bit bit name description 0 not used. normally a 1mv weight. 1 not used. normally a 2mv weight. 2 not used. normally a 4mv weight. 3 not used. normally a 8mv weight. 4 not used. normally a 16mv weight. 5 iinp voltage, dacv 0 0 = adds 0mv of iinp voltage. 1 = adds 12.8mv of iinp voltage. 6 iinp voltage, dacv 1 0 = adds 0mv of iinp voltage. 1 = adds 25.6mv of iinp voltage. 7 iinp voltage, dacv 2 0 = adds 0mv of iinp voltage. 1 = adds 51.2mv of iinp voltage. 8 iinp voltage, dacv 3 0 = adds 0mv of iinp voltage. 1 = adds 102.4mv of iinp voltage. 9 iinp voltage, dacv 4 0 = adds 0mv of iinp voltage. 1 = adds 204.8mv of iinp voltage. 10 iinp voltage, dacv 5 0 = adds 0ma of iinp voltage. 1 = adds 409.6mv of iinp voltage.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 23 dc-dc converter the MAX17035/max17435/max17535 employ a synchronous step-down dc-dc converter with an n-channel, high-side mosfet switch and an n-channel low-side synchronous rectifier. the MAX17035/max17435/max17535 feature a pseudo-fixed-frequency, current-mode control scheme with cycle-by-cycle current limit. the controllers constant off-time (t off ) is calculated based on v dcin , v csin , and a time constant with a minimum value of 300ns. the MAX17035/max17435/max17535 can also operate in discontinuous conduction mode for improved light-load efficiency. the operation of the dc-to-dc controller is determined by the following five comparators as shown in the functional diagram in figure 2: u the imin comparator sets the peak inductor current in discontinuous mode. imin compares the control signal (lvc) against 100mv (typ). when lvc voltage is less than 100mv, dhi and dlo are both low. u the ccmp comparator is used for current-mode regulation in continuous conduction mode. ccmp compares lvc against the charging current feedback signal (csi). the comparator output is high and the high-side mosfet on-time is terminated when the csi voltage is higher than lvc. u the imax comparator provides a cycle-by-cycle current limit. imax compares csi to 2v (corresponding to 10a when rs2 = 10m i ). the comparator output is high and the high-side mosfet on-time is terminated when the current-sense signal exceeds 10a. a new cycle cannot start until the imax comparator output goes low. u the zcmp comparator provides zero-crossing detection during discontinuous conduction. zcmp compares the current-sense feedback signal to 500ma (rs2 = 10m i ). when the inductor current is lower than the 500ma threshold, the comparator output is high and dlo is turned off. u the ovp comparator. the MAX17035/max17435/ max17535 incorporate a comparator to check for the battery voltage 400mv above the set point and, if that condition is detected, it disables charging. ccv, cci, ccs, and lvc control blocks the MAX17035/max17435/max17535 control input current (ccs control loop), charge current (cci control loop), or charge voltage (ccv control loop), depending on the operating condition. the three control loops, ccv, cci, and ccs are brought together internally at the lowest voltage clamp (lvc) amplifier. the output of the lvc amplifier is the feedback control signal for the dc-dc controller. the minimum voltage at the ccv, cci, or ccs appears at the output of the lvc amplifier and clamps the other control loops to within 0.3v above the control point. clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the compensation section). continuous conduction mode with sufficient charge current, the MAX17035/max17435/ max17535s inductor current never crosses zero, which is defined as continuous conduction mode. the regulator switches at 1.2mhz (nominal) if it is not in dropout (v csin < 0.88 o v dcin ). the controller starts a new cycle by turning on the high-side mosfet and turning off the low-side mosfet. when the charge current feedback signal (csi) is greater than the control point (lvc), the ccmp comparator output goes high and the controller initiates the off-time by turning off the high-side mosfet and turning on the low-side mosfet. the operating frequency is governed by the off-time and is dependent upon v csin and v dcin . at the end of the fixed off-time, the controller initiates a new cycle if the control point (lvc) is greater than 150mv, and the peak charge current is less than the cycle-by-cycle current limit. restated another way, imin table 8. iinpvoltage() (0x3e) (continued) bit bit name description 11 iinp voltage, dacv 6 0 = adds 0mv of iinp voltage. 1 = adds 819.2v of iinp voltage to a maximum of 2.20v. 12 iinp voltage, dacv 7 0 = adds 0mv of iinp voltage. 1 = adds 1.6384v of iinp voltage to a maximum of 2.20v. 13 not used. normally a 8192mv weight. 14 not used. normally a 16384mv weight. 15 not used. normally a 32768mv weight.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 24 _____________________________________________________________________________________ must be high, max must be low, and ovp must be low for the controller to initiate a new cycle. if the peak inductor current exceeds imax comparator threshold or the output voltage exceeds the ovp threshold, then the on-time is terminated. the cycle-by-cycle current limit effectively protects against overcurrent and short-circuit faults. if during the off-time the inductor current goes to zero, the zcmp comparator output pulls high, turning off the low-side mosfet. both the high- and low-side mosfets are turned off until another cycle is ready to begin. the MAX17035/max17435/max17535 enter into the discontinuous conduction mode (see the discontinuous conduction section). the on-time is calculated according to the following equation: ripple on cssn batt l i t v - v = where: batt off ripple v t i l = there is a 0.3 f s minimum off-time when the (v dcin - v batt ) differential becomes too small. if v batt r 0.88 x v dcin , then the threshold for minimum off-time is reached and the off-time is fixed at 0.27 f s. the switching frequency in this mode varies according to the equation: ripple off cssn batt 1 f l i t v - v = + discontinuous conduction the MAX17035/max17435/max17535 can also operate in discontinuous conduction mode to ensure that the inductor current is always positive. the MAX17035/ max17435/max17535 enter discontinuous conduction mode when the output of the lvc control point falls below 150mv. for rs2 = 10m i , this corresponds to 375ma: 1 dis 2 150mv i 375ma 20 rs2 = = where charge current for rs2 = 10m i . in discontinuous mode, a new cycle is not started until the lvc voltage rises above 150mv. discontinuous mode operation can occur during conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the ccs control loop, or when the charger is in constant-voltage mode with a nearly full battery pack. compensation the cci loop is internally compensated. the ccv and the ccs share the external compensation capacitor. the control loop, which is dominant, uses the external compensation cap and the one that is not used uses an internal compensation capacitor. ccv loop compensation the simplified schematic in figure 6 is sufficient to describe the operation of the MAX17035/max17435/ max17535 when the voltage loop (ccv) is in control. the required compensation network is a pole-zero pair formed with c cv and r cv, which is an internal 1.7k i . the pole is necessary to roll off the voltage loops response at low frequency; c cv = 330pf is sufficient for most applications. mosfet drivers the dhi and dlo outputs are optimized for driving moderate-sized power mosfets. the mosfet drive capability is the same for both the low-side and high- sides switches. this is consistent with the variable duty factor that occurs in the notebook computer environment where the battery voltage changes over a wide range. there must be a low-resistance, low-inductance path from the dlo driver to the mosfet gate to prevent shoot- through. otherwise, the sense circuitry in the MAX17035/ max17435/max17535 interprets the mosfet gate as off while there is still charge left on the gate. use very short, wide traces measuring 10 squares to 20 squares or less (1.25mm to 2.5mm wide if the mosfet is 25mm from the device). unlike the dlo output, the dhi output uses a 50ns (typ) delay time to prevent the low-side mosfet from turning on until dhi is fully off. the same considerations should be used for routing the dhi signal to the high-side mosfet. figure 6. ccv loop diagram c cv c out r cv r l r esr r ogmv ccv batt gmv ref gm out
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 ______________________________________________________________________________________ 25 the high-side driver (dhi) swings from lx to 5v above lx (bst) and has a typical impedance of 1.5 i sourcing and 0.8 i sinking. the low-side driver (dlo) swings from dlov to ground and has a typical impedance of 3 i sinking and 3 i sourcing. this helps prevent dlo from being pulled up when the high-side switch turns on due to capacitive coupling from the drain to the gate of the low-side mosfet. this places some restrictions on the mosfets that can be used. using a low-side mosfet with smaller gate-to-drain capacitance can prevent these problems. design procedure mosfet selection choose the n-channel mosfets according to the maxi- mum required charge current. low-current applications usually require less attention. the high-side mosfet (n1) must be able to dissipate the resistive losses plus the switching losses at both v dci;min) and v dcin(max) . calculate both these sums. ideally, the losses at v dcin(min) should be roughly equal to losses at v dcin(max) with lower losses in between. if the losses at v dcin(min) are significantly higher than the losses at v dcin(max) , consider increasing the size of m1. conversely, if the losses at v dcin(max) are significantly higher than the losses at v in(min) , consider reducing the size of m1. if dcin does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin so, dpak, or d 2 pak), and is reasonably priced. make sure that the dlo gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems can occur. select devices that have short turn-off times, and make sure that: n2(t doff(max) ) - n1(t don(min) ) < 40ns, and n1(t doff(max) ) - n2(t don(min) ) < 40ns failure to do so could result in efficiency-reducing shoot- through currents. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case power dissipation (pd) due to resistance occurs at the minimum supply voltage: batt load ds(on) dcin 2 v i pd(high - side) r v 2 ? ? ? ? = ? ? ? ? ? ? ? ? generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power- dissipation limits often limits how small the mosfet can be. the optimum occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f switching- loss equation. if the high-side mosfet that was chosen for adequate r ds(on) at low supply voltages becomes extraordinarily hot when subjected to v in(max) , then choose a mosfet with lower losses. calculating the power dissipation in m1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on n1: 2 dcin(max) rss sw load gate v c f i pd(hs_switching) 2 i = where c rss is the reverse transfer capacitance of n1 and i gate is the peak gate-drive source/sink current (3.3a sourcing and 5a sinking). for the low-side mosfet (n2), the worst-case power dissipation always occurs at maximum input voltage: batt load ds(on) dcin 2 v i pd(low - side) 1- r v 2 ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? inductor selection the charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. for optimum efficiency, choose the inductance according to the following equation: l = v batt o t off /(0.3 x i chg ) this sets the ripple current to 1/3 the charge current and results in a good balance between inductor size and efficiency. higher inductor values decrease the ripple current. smaller inductor values require high saturation current capabilities and degrade efficiency. inductor l1 must have a saturation current rating of at least the maximum charge current plus 1/2 the ripple current ( d il): i sat = i chg + (1/2) d il
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 26 _____________________________________________________________________________________ the ripple current is determined by: d il = v batt o t off /l where: t off = 2.5 f s (v dcin - v batt )/ v dcin for v batt < 0.88 v dcin or: t off = 0.3 f s for v batt > 0.88 v dcin input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. nontantalum chemistries (ceramic, aluminum, or os- con) are preferred due to their resilience to power-up surge currents: ( ) rms chg batt dcin batt dcin v v - v i i v ? ? ? ? = ? ? ? ? the input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10 n c. the maximum ripple current occurs at 50% duty factor or v dcin = 2 x v batt , which equates to 0.5 x i chg . if the application of interest does not achieve the maximum value, size the input capacitors according to the worst- case conditions. output capacitor selection the output capacitor absorbs the inductor ripple current and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. as such, both capacitance and esr are important parameters in specifying the output capacitor as a filter and to the ensure stability of the dc-to-dc converter. see the compensation section. beyond the stability requirements, it is often sufficient to make sure that the output capacitors esr is much lower than the batterys esr. either tantalum or ceramic capacitors can be used on the output. ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. for most applications the output cap can be as low as 4.7 f f. if the output voltage is low and the input voltage is high, the output capacitance may need to be increased. applications information layout and bypassing bypass dcin with a 0.1 f f ceramic to ground (figure 1). n3 and q1a protect the MAX17035/max17435/ max17535 when the dc power source input is reversed. a signal diode for d2 is adequate because dcin only powers the ldo and the internal reference. bypass vcc, dcin, ldo, dhi, and vaa, as shown in figure 1. good pcb layout is required to achieve specified noise immunity, efficiency, and stable performance. the pcb layout artist must be given explicit instructions preferably, a sketch showing the placement of the power switching components and high current routing. refer to the pcb layout in the MAX17035/max17435/max17535 evaluation kit for examples. a ground plane is essential for optimum performance. in most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. use the top layer for high current connections, the bottom layer for quiet connections, and the inner layers for an uninterrupted ground plane. use the following step-by-step guide: 1) place the high-power connections first, with their grounds adjacent: u minimize the current-sense resistor trace lengths, and ensure accurate current sensing with kelvin connections. u minimize ground trace lengths in the high-current paths. u minimize other trace lengths in the high-current paths. u use > 5mm wide traces in the high-current paths. u connect c1 and c2 to high-side mosfet (10mm max length). u minimize the lx node (mosfets, rectifier cathode, inductor (15mm max length)). keep lx on one side of the pcb to reduce emi radiation.
high-frequency, low-cost smbus chargers MAX17035/max17435/max17535 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 27 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. ideally, surface-mount power components are flush against one another with their ground terminals almost touching. these high-current grounds are then con - nected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. the resulting top-layer subground plane is connected to the normal inner-layer ground plane at the paddle. other high- current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all pcb layout problems. place the ic and signal components. keep the main switching node (lx node) away from sensitive analog components (current-sense traces and ref capacitor). important: the ic must be no further than 10mm from the current-sense resistors. quiet connections to ref, ccv, cci, acin, and dcin should be returned to a separate ground (gnd) island. the appropriate traces are marked on the schematic with the () ground symbol. there is very little current flowing in these traces, so the ground island need not be very large. when placed on an inner layer, a sizable ground island can help simplify the layout because the low current connections can be made through vias. the ground pad on the backside of the package should also be connected to this quiet ground island. keep the gate drive traces (dhi and dlo) as short as possible (l < 20mm), and route them away from the current-sense lines and ref. these traces should also be relatively wide (w > 1.25mm). place ceramic bypass capacitors close to the ic. the bulk capacitors can be placed further away. place the current-sense input filter capacitors under the part, connected directly to the gnd pin. use a single-point star ground placed directly below the part at the pgnd pin. connect the power ground (ground plane) and the quiet ground island at this location. refer to the MAX17035 ev kit layout for a layout example. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 24 tqfn t2444-4 21-0139 chip information process: bicmos

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